1. Field of the Invention
This invention relates generally to the low cost fabrication of hermetic thin packagings (HTPs) of high density power semiconductors and, more specifically, to methods for providing such fabrication by batch assembly. The primary thrust of the batch assembly concept is to maintain integrity of chip arrays, package containment arrays and package lid arrays as far into the fabrication and final assembly process as is technologically and economically feasible, thereby avoiding such detrimental aspects of production as excessive handling, specialized treatment of individualized components, the necessity of employing solder preforms, and reliance upon specially fabricated frames and/or individual die apparatus.
2. Background Information
In a previously known approach for construction of the high density power packages known as HTPs, achievement of a packing density amounting to 42% of the theoretically achievable silicon area availability was deemed noteworthy. There have been, however, several economic drawbacks in some of the HTP material and process steps. Thus, throughout development of the hereinafter disclosed batch fabrication processes, a number of drawbacks to the previous approach were targeted for special attention and were systematically optimized, if not eliminated entirely. The drawbacks of concern are primarily those that give rise to excessive component handling, such as in fabricating individual ceramic lids, casings or cups for the packages, and preparing device and device mounting at an individual die level. Other drawbacks of concern include excessive set up times and materials, as well as the requirement to use solder preforms or the compelled use of copper/molybdenum/copper (Cu/Mo/Cu) frames for construction of the cup in which the chip is die mounted.
The instant invention employs a number of processes which derive their high utility and economic value from new developments and technology such as that noted in the aforementioned application Ser. No. 07/603,495, pending application. For this reason, one skilled in the art should be aware of the existence of such technology so that a concise and comprehensive explanation of the instant invention may ensue.
In one aspect of the invention, thermocompression bonding of copper foil conductors to the aluminum metallization of a power semiconductor chip, disclosed in the referenced application Ser. No. 07/603,495, pending application, for the individual chip device level, is extended to the multi-chip device level or batch manufacture. A full appreciation of the teachings regarding thermocompression bonded copper foil conductors may be obtained from the article entitled: "MCT Power Packaging" by C. A. Neugebauer, J. F. Burgess, H. H. Glascock, V. A. K. Temple and D. L. Watrous as presented in the Proceedings of the 40th IEEE ETCT, May 1990, which is herein incorporated by reference.
The development of the HTP packaging approach has resulted in a hermetic package outline not much bigger than the chip itself. This unique packaging was achieved by replacing the traditional aluminum wire bonds with small copper spheres (approximately 0.040 in. in diameter), which make connections to the chip topside contact (typically gate and anode) through holes extending directly through the ceramic (alumina) package lid. Electrical contact is made to the chip through bonding, as by means of thermocompression and solders, and contact to the lid is made by means of hermetically direct-bonded copper (DBC) foil. Attainment of hermeticity is adequately disclosed in the aforementioned Neugebauer et al. IEEE article and elsewhere, such as in H. F. Webster U.S. patent application Ser. No. 07/454,548, filed Dec. 21, 1989, pending application, entitled "CERAMIC-TO-CONDUCTING-LEAD HERMETIC SEAL" and in V. A. K. Temple et al. U.S. patent application Ser. No. 07/367,525, filed Jun. 16, 1989, entitled "HERMETIC PACKAGE HAVING A LEAD EXTENDING THROUGH AN APERTURE IN THE PACKAGE LID AND PACKAGE SEMICONDUCTOR CHIP", U.S. Pat. No. 5,069,879. Essentially, the aforementioned Neugebauer et al. article and the Webster and Temple et al. applications teach the process of hermetically sealing apertures in a ceramic package lid by a direct bond between the ceramic lid and a copper foil which extends across apertures in the lid. Such direct bond copper processes as used to form the copper foil-to-ceramic seal, or bonds, are also described in U.S. Pat. Nos. 3,744,120, 3,854,892, and 3,911,553 all issued to Burgess et al.; U.S. Pat. No. 4,129,243 issued to Cusano et al.; U.S. Pat. No. 4,409,278 issued to Jochym; and U.S. Pat. No. 4,563,383 issued to Kuneman et al. These Burgess et al., Cusano et al. and Jochym patents are incorporated herein by reference, and teach the use of copper-copper oxide, nickel-nickel oxide, cobalt-cobalt oxide, iron-iron oxide and copper-copper sulfide eutectics to form direct bonds of the respective substances. The bond contemplated in the instant invention is formed by a copper-copper oxide eutectic mixture which wets both metallic copper and ceramic materials such as aluminum and beryllia and which bonds the members together upon solidification. The copper-copper oxide eutectic process is well known to fabricators of encapsulated devices and modules in the electronics field. A salient aspect of the Neugebauer et al. application Ser. No. 07/603,495, pending applicaiton, teaching is the copper foil conductor thermocompression bonding to the chip aluminum metallization which comprises the chip contact padding. After the composite foil is fabricated, it is etched or stamped into a desired shape which may contain voids or slots (i.e., a lacy construction) in order to reduce thermal expansion mismatch after it is bonded to a chip pad. A special marginal frame design is used to acquire a plurality of leaves in the foil laminate, which leaves extend from the marginal frame to connect with larger foil areas located within the framework. When the proper pattern of foil has been achieved, the foil is thermocompression bonded to the top aluminum padding of the chip. By design, the chip padding aluminum is supplied in excess, and gold in a copper/chromium/gold (Cu/Cr/Au) foil laminate is supplied in modest amounts. The aluminum is not fully consumed by the reaction, but all of the gold on the foil laminate is converted to a stable (AuAl.sub.2) intermetallic phase. The remaining boundary layer of excess aluminum metallization on the chip forms a buffer and prevents direct contact with, and delamination from, the silicon chip by the intermetallic; concurrently, an earlier-deposited chromium film on the copper foil forms a barrier layer that prevents copper diffusion into the aluminum film or gold-aluminum matrix, thus avoiding formation of copper-aluminum intermetallics. Once the thermocompression bonding to the chip is completed, the foil frame is excised and the marginal leaves of the foil are bent or retroflexed over the chip margins, superimposing them over the bonded foil portions (central of the frame) from which they extend. The retroflexed leaves provide a stress relief contact for through-the-lid connectors/conductors such as the copper spheres disclosed in the aforementioned Neugebauer et al. IEEE article and hereinafter.